Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 A-75
PERFORMANCE-MONITORING EVENTS
60H See
Table
18-11
and
Table
18-12
BUS_REQUEST_
OUTSTANDING.
(Core and Bus
Agents)
Outstanding
cacheable data
read bus
requests
duration
This event counts the number of pending
full cache line read transactions on the bus
occurring in each cycle. A read transaction
is pending from the cycle it is sent on the
bus until the full cache line is received by
the processor.
The event counts only full-line cacheable
read requests from either the L1 data
cache or the L2 prefetchers. It does not
count Read for Ownership transactions,
instruction byte fetch transactions, or any
other bus transaction.
61H See
Table
18-12.
BUS_BNR_DRV.
(Bus Agents)
Number of Bus
Not Ready
signals
asserted
This event counts the number of Bus Not
Ready (BNR) signals that the processor
asserts on the bus to suspend additional
bus requests by other bus agents.
A bus agent asserts the BNR signal when
the number of data and snoop
transactions is close to the maximum that
the bus can handle. To obtain the number
of bus cycles during which the BNR signal
is asserted, multiply the event count by
two.
While this signal is asserted, new
transactions cannot be submitted on the
bus. As a result, transaction latency may
have higher impact on program
performance.
Table A-6. Non-Architectural Performance Events
in Processors Based on Intel Core Microarchitecture (Contd.)
Event
Num
Umask
Value Event Name Definition
Description and
Comment