Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

A-76 Vol. 3
PERFORMANCE-MONITORING EVENTS
62HSee
Table
18-12
BUS_DRDY_
CLOCKS.(Bus
Agents)
Bus cycles
when data is
sent on the bus
This event counts the number of bus
cycles during which the DRDY (Data
Ready) signal is asserted on the bus. The
DRDY signal is asserted when data is sent
on the bus. With the 'THIS_AGENT' mask
this event counts the number of bus
cycles during which this agent (the
processor) writes data on the bus back to
memory or to other bus agents. This
includes all explicit and implicit data
writebacks, as well as partial writes.
With the 'ALL_AGENTS' mask, this event
counts the number of bus cycles during
which any bus agent sends data on the
bus. This includes all data reads and writes
on the bus.
63HSee
Table
18-11
and
Table
18-12
BUS_LOCK_
CLOCKS.(Core and
Bus Agents)
Bus cycles
when a LOCK
signal asserted
This event counts the number of bus
cycles, during which the LOCK signal is
asserted on the bus. A LOCK signal is
asserted when there is a locked memory
access, due to:
• uncacheable memory
• locked operation that spans two cache
lines
• page-walk from an uncacheable page
table
Bus locks have a very high performance
penalty and it is highly recommended to
avoid such accesses.
64HSee
Table
18-11
BUS_DATA_
RCV.(Core)
Bus cycles
while processor
receives data
This event counts the number of bus
cycles during which the processor is busy
receiving data.
65HSee
Table
18-11
and
Table
18-12
BUS_TRANS_BRD.(
Core and Bus
Agents)
Burst read bus
transactions
This event counts the number of burst
read transactions including:
• L1 data cache read misses (and L1 data
cache hardware prefetches)
• L2 hardware prefetches by the DPL and
L2 streamer
• IFU read misses of cacheable lines.
It does not include RFO transactions.
Table A-6. Non-Architectural Performance Events
in Processors Based on Intel Core Microarchitecture (Contd.)
Event
Num
Umask
Value Event Name Definition
Description and
Comment