Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 A-77
PERFORMANCE-MONITORING EVENTS
66H See
Table
18-11
and
Table
18-12.
BUS_TRANS_RFO.(
Core and Bus
Agents)
RFO bus
transactions
This event counts the number of Read For
Ownership (RFO) bus transactions, due to
store operations that miss the L1 data
cache and the L2 cache. It also counts RFO
bus transactions due to locked operations.
67H See
Table
18-11
and
Table
18-12.
BUS_TRANS_WB.
(Core and Bus
Agents)
Explicit
writeback bus
transactions
This event counts all explicit writeback bus
transactions due to dirty line evictions. It
does not count implicit writebacks due to
invalidation by a snoop request.
68H See
Table
18-11
and
Table
18-12
BUS_TRANS_
IFETCH.(Core and
Bus Agents)
Instruction-
fetch bus
transactions
This event counts all instruction fetch full
cache line bus transactions.
69HSee
Table
18-11
and
Table
18-12
BUS_TRANS_
INVAL.(Core and
Bus Agents)
Invalidate bus
transactions
This event counts all invalidate
transactions. Invalidate transactions are
generated when:
• A store operation hits a shared line in
the L2 cache.
• A full cache line write misses the L2
cache or hits a shared line in the L2
cache.
6AH See
Table
18-11
and
Table
18-12
BUS_TRANS_
PWR.(Core and Bus
Agents)
Partial write
bus transaction
This event counts partial write bus
transactions.
6BH See
Table
18-11
and
Table
18-12
BUS_TRANS
_P.(Core and Bus
Agents)
Partial bus
transactions
This event counts all (read and write)
partial bus transactions.
Table A-6. Non-Architectural Performance Events
in Processors Based on Intel Core Microarchitecture (Contd.)
Event
Num
Umask
Value Event Name Definition
Description and
Comment