Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

A-78 Vol. 3
PERFORMANCE-MONITORING EVENTS
6CH See
Table
18-11
and
Table
18-12
BUS_TRANS_IO.(C
ore and Bus
Agents)
IO bus
transactions
This event counts the number of
completed I/O bus transactions as a result
of IN and OUT instructions. The count does
not include memory mapped IO.
6DH See
Table
18-11
and
Table
18-12
BUS_TRANS_
DEF.(Core and Bus
Agents)
Deferred bus
transactions
This event counts the number of deferred
transactions.
6EHSee
Table
18-11
and
Table
18-12
BUS_TRANS_
BURST.(Core and
Bus Agents)
Burst (full
cache-line) bus
transactions
This event counts burst (full cache line)
transactions including:
•Burst reads
•RFOs
•Explicit writebacks
•Write combine lines
6FH See
Table
18-11
and
Table
18-12
BUS_TRANS_
MEM.(Core and Bus
Agents)
Memory bus
transactions
This event counts all memory bus
transactions including:
• Burst transactions
• Partial reads and writes - invalidate
transactions
The BUS_TRANS_MEM count is the sum of
BUS_TRANS_BURST, BUS_TRANS_P and
BUS_TRANS_IVAL.
70H See
Table
18-11
and
Table
18-12
BUS_TRANS_
ANY.(Core and Bus
Agents)
All bus
transactions
This event counts all bus transactions. This
includes:
• Memory transactions
• IO transactions (non memory-mapped)
•Deferred transaction completion
• Other less frequent transactions, such
as interrupts
Table A-6. Non-Architectural Performance Events
in Processors Based on Intel Core Microarchitecture (Contd.)
Event
Num
Umask
Value Event Name Definition
Description and
Comment