Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 A-79
PERFORMANCE-MONITORING EVENTS
77H See
Table
18-11
and
Table
18-15
EXT_SNOOP.
(Bus Agents, Snoop
Response)
External
snoops
This event counts the snoop responses to
bus transactions. Responses can be
counted separately by type and by bus
agent.
With the 'THIS_AGENT' mask, the event
counts snoop responses from this
processor to bus transactions sent by this
processor. With the 'ALL_AGENTS' mask
the event counts all snoop responses seen
on the bus.
78H See
Table
18-11
and
Table
18-16
CMP_SNOOP.(Core,
Snoop Type)
L1 data cache
snooped by
other core
This event counts the number of times the
L1 data cache is snooped for a cache line
that is needed by the other core in the
same processor. The cache line is either
missing in the L1 instruction or data
caches of the other core, or is available for
reading only and the other core wishes to
write the cache line.
The snoop operation may change the
cache line state. If the other core issued a
read request that hit this core in E state,
typically the state changes to S state in
this core. If the other core issued a read
for ownership request (due a write miss or
hit to S state) that hits this core's cache
line in E or S state, this typically results in
invalidation of the cache line in this core. If
the snoop hits a line in M state, the state is
changed at a later opportunity.
These snoops are performed through the
L1 data cache store port. Therefore,
frequent snoops may conflict with
extensive stores to the L1 data cache,
which may increase store latency and
impact performance.
7AH See
Table
18-12
BUS_HIT_DRV.
(Bus Agents)
HIT signal
asserted
This event counts the number of bus
cycles during which the processor drives
the HIT# pin to signal HIT snoop response.
Table A-6. Non-Architectural Performance Events
in Processors Based on Intel Core Microarchitecture (Contd.)
Event
Num
Umask
Value Event Name Definition
Description and
Comment