Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

A-80 Vol. 3
PERFORMANCE-MONITORING EVENTS
7BH See
Table
18-12
BUS_HITM_DRV.
(Bus Agents)
HITM signal
asserted
This event counts the number of bus
cycles during which the processor drives
the HITM# pin to signal HITM snoop
response.
7DH See
Table
18-11
BUSQ_EMPTY.
(Core)
Bus queue
empty
This event counts the number of cycles
during which the core did not have any
pending transactions in the bus queue. It
also counts when the core is halted and
the other core is not halted.
This event can count occurrences for this
core or both cores.
7EH See
Table
18-11
and
Table
18-12
SNOOP_STALL_
DRV.(Core and Bus
Agents)
Bus stalled for
snoops
This event counts the number of times
that the bus snoop stall signal is asserted.
To obtain the number of bus cycles during
which snoops on the bus are prohibited,
multiply the event count by two.
During the snoop stall cycles, no new bus
transactions requiring a snoop response
can be initiated on the bus. A bus agent
asserts a snoop stall signal if it cannot
response to a snoop request within three
bus cycles.
7FH See
Table
18-11
BUS_IO_WAIT.
(Core)
IO requests
waiting in the
bus queue
This event counts the number of core
cycles during which IO requests wait in the
bus queue. With the SELF modifier this
event counts IO requests per core.
With the BOTH_CORE modifier, this event
increments by one for any cycle for which
there is a request from either core.
80H 00H L1I_READS Instruction
fetches
This event counts all instruction fetches,
including uncacheable fetches that bypass
the Instruction Fetch Unit (IFU).
81H 00H L1I_MISSES Instruction
Fetch Unit
misses
This event counts all instruction fetches
that miss the Instruction Fetch Unit (IFU)
or produce memory requests. This
includes uncacheable fetches.
An instruction fetch miss is counted only
once and not once for every cycle it is
outstanding.
Table A-6. Non-Architectural Performance Events
in Processors Based on Intel Core Microarchitecture (Contd.)
Event
Num
Umask
Value Event Name Definition
Description and
Comment