Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 A-81
PERFORMANCE-MONITORING EVENTS
82H 02H ITLB.SMALL_MISS ITLB small page
misses
This event counts the number of
instruction fetches from small pages that
miss the ITLB.
82H 10H ITLB.LARGE_MISS ITLB large page
misses
This event counts the number of
instruction fetches from large pages that
miss the ITLB.
82H 40H ITLB.FLUSH ITLB flushes This event counts the number of ITLB
flushes. This usually happens upon CR3 or
CR0 writes, which are executed by the
operating system during process switches.
82H 12H ITLB.MISSES ITLB misses This event counts the number of
instruction fetches from either small or
large pages that miss the ITLB.
83H 02H INST_QUEUE.FULL Cycles during
which the
instruction
queue is full
This event counts the number of cycles
during which the instruction queue is full.
In this situation, the core front-end stops
fetching more instructions. This is an
indication of very long stalls in the back-
end pipeline stages.
86H 00HCYCLES_L1I_
MEM_STALLED
Cycles during
which
instruction
fetches stalled
This event counts the number of cycles for
which an instruction fetch stalls, including
stalls due to any of the following reasons:
• instruction Fetch Unit cache misses
• instruction TLB misses
• instruction TLB faults
87H 00H ILD_STALL Instruction
Length Decoder
stall cycles due
to a length
changing prefix
This event counts the number of cycles
during which the instruction length
decoder uses the slow length decoder.
Usually, instruction length decoding is
done in one cycle. When the slow decoder
is used, instruction decoding requires 6
cycles.
Table A-6. Non-Architectural Performance Events
in Processors Based on Intel Core Microarchitecture (Contd.)
Event
Num
Umask
Value Event Name Definition
Description and
Comment