Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 18-49
DEBUGGING AND PERFORMANCE MONITORING
• PC (pin control) flag (bit 19) — When set, the logical processor toggles the
PMi pins and increments the counter when performance-monitoring events
occur; when clear, the processor toggles the PMi pins when the counter
overflows. The toggling of a pin is defined as assertion of the pin for a single bus
clock followed by deassertion.
• INT (APIC interrupt enable) flag (bit 20) — When set, the logical processor
generates an exception through its local APIC on counter overflow.
• EN (Enable Counters) Flag (bit 22) — When set, performance counting is
enabled in the corresponding performance-monitoring counter; when clear, the
corresponding counter is disabled. The event logic unit for a UMASK must be
disabled by setting IA32_PERFEVTSELx[bit 22] = 0, before writing to
IA32_PMCx.
• INV (invert) flag (bit 23) — Inverts the result of the counter-mask comparison
when set, so that both greater than and less than comparisons can be made.
• Counter mask (CMASK) field (bits 24 through 31) — When this field is not
zero, a logical processor compares this mask to the events count of the detected
microarchitectural condition during a single cycle. If the event count is greater
than or equal to this mask, the counter is incremented by one. Otherwise the
counter is not incremented.
This mask is intended for software to characterize microarchitectural conditions
that can count multiple occurrences per cycle (for example, two or more instruc-
tions retired per clock; or bus queue occupations). If the counter-mask field is 0,
then the counter is incremented each cycle by the event count associated with
multiple occurrences.
18.13.2 Additional Architectural Performance Monitoring Extensions
The enhanced features provided by architectural performance monitoring version 2
include the following:
• Fixed-function performance counter register and associated control
register — Three of the architectural performance events are counted using
three fixed-function MSRs (IA32_FIXED_CTR0 through IA32_FIXED_CTR2). Each
of the fixed-function PMC can count only one architectural performance event.
Configuring the fixed-function PMCs is done by writing to bit fields in the MSR
(IA32_FIXED_CTR_CTRL) located at address 38DH. Unlike configuring
performance events for general-purpose PMCs (IA32_PMCx) via UMASK field in
(IA32_PERFEVTSELx), configuring, programming IA32_FIXED_CTR_CTRL for
fixed-function PMCs do not require any UMASK.
• Simplified event programming — Most frequent operation in programming
performance events are enabling/disabling event counting and checking the
status of counter overflows. Architectural performance event version 2 provides
three architectural MSRs: