Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 A-109
PERFORMANCE-MONITORING EVENTS
EIST transitions are commonly initiated by
OS, but can be initiated by HW internally. For
example: CxE states are C-states (C1,C2,C3…)
which not only place the CPU into a sleep
state by turning off the clock and other
components, but also lower the voltage
(which reduces the leakage power
consumption). The same is true for thermal
throttling transition which uses EIST
internally.
3BH C0H THERMAL_TRIP Number of
thermal trips
This event counts the number of thermal
trips. A thermal trip occurs whenever the
processor temperature exceeds the thermal
trip threshold temperature. Following a
thermal trip, the processor automatically
reduces frequency and voltage. The
processor checks the temperature every
millisecond, and returns to normal when the
temperature falls below the thermal trip
threshold temperature.
3CH 00H CPU_CLK_UNH
ALTED.CORE_P
Core cycles
when core is not
halted
This event counts the number of core cycles
while the core is not in a halt state. The core
enters the halt state when it is running the
HLT instruction. This event is a component in
many key event ratios.
In mobile systems the core frequency may
change from time to time. For this reason this
event may have a changing ratio with regards
to time. In systems with a constant core
frequency, this event can give you a
measurement of the elapsed time while the
core was not in halt state by dividing the
event count by the core frequency.
-This is an architectural performance event.
- The event CPU_CLK_UNHALTED.CORE_P is
counted by a programmable counter.
- The event CPU_CLK_UNHALTED.CORE is
counted by a designated fixed counter,
leaving the two programmable counters
available for other events
Table A-7. Non-Architectural Performance Events for Intel Atom Processors
Event
Num.
Umask
Value Event Name Definition Description and Comment