Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

A-110 Vol. 3
PERFORMANCE-MONITORING EVENTS
3CH 01H CPU_CLK_UNH
ALTED.BUS
Bus cycles
when core is not
halted
This event counts the number of bus cycles
while the core is not in the halt state. This
event can give you a measurement of the
elapsed time while the core was not in the
halt state, by dividing the event count by the
bus frequency. The core enters the halt state
when it is running the HLT instruction.
The event also has a constant ratio with
CPU_CLK_UNHALTED.REF event, which is the
maximum bus to processor frequency ratio.
Non-halted bus cycles are a component in
many key event ratios.
3CH 02H CPU_CLK_UNH
ALTED.NO_OTH
ER
Bus cycles
when core is
active and the
other is halted
This event counts the number of bus cycles
during which the core remains non-halted,
and the other core on the processor is halted.
This event can be used to determine the
amount of parallelism exploited by an
application or a system. Divide this event
count by the bus frequency to determine the
amount of time that only one core was in use.
40H 21H L1D_CACHE.LD L1 Cacheable
Data Reads
This event counts the number of data reads
from cacheable memory.
40H 22H L1D_CACHE.ST L1 Cacheable
Data Writes
This event counts the number of data writes
to cacheable memory
60H See
Table
18-11
and
Table
18-12
BUS_REQUEST_
OUTSTANDING
Outstanding
cacheable data
read bus
requests
duration
This event counts the number of pending full
cache line read transactions on the bus
occurring in each cycle. A read transaction is
pending from the cycle it is sent on the bus
until the full cache line is received by the
processor. NOTE: This event is thread-
independent and will not provide a count per
logical processor when AnyThr is disabled
Table A-7. Non-Architectural Performance Events for Intel Atom Processors
Event
Num.
Umask
Value Event Name Definition Description and Comment