Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

A-112 Vol. 3
PERFORMANCE-MONITORING EVENTS
64H See
Table
18-11
BUS_DATA_RCV Bus cycles while
processor
receives data
This event counts the number of cycles
during which the processor is busy receiving
data. NOTE: This event is thread-independent
and will not provide a count per logical
processor when AnyThr is disabled
65H See
Table
18-11
and
Table
18-12
BUS_TRANS_B
RD
Burst read bus
transactions
This event counts the number of burst read
transactions including:
- L1 data cache read misses (and L1 data
cache hardware prefetches)
- L2 hardware prefetches by the DPL and L2
streamer
- IFU read misses of cacheable lines.
It does not include RFO transactions.
66H See
Table
18-11
and
Table
18-12
BUS_TRANS_RF
O
RFO bus
transactions
This event counts the number of Read For
Ownership (RFO) bus transactions, due to
store operations that miss the L1 data cache
and the L2 cache. This event also counts RFO
bus transactions due to locked operations.
67H See
Table
18-11
and
Table
18-12
BUS_TRANS_W
B
Explicit
writeback bus
transactions
This event counts all explicit writeback bus
transactions due to dirty line evictions. It
does not count implicit writebacks due to
invalidation by a snoop request.
68H See
Table
18-11
and
Table
18-12
BUS_TRANS_IF
ETCH
Instruction-
fetch bus
transactions.
This event counts all instruction fetch full
cache line bus transactions.
69H See
Table
18-11
and
Table
18-12
BUS_TRANS_IN
VAL
Invalidate bus
transactions
This event counts all invalidate transactions.
Invalidate transactions are generated when:
- A store operation hits a shared line in the L2
cache.
- A full cache line write misses the L2 cache
or hits a shared line in the L2 cache.
Table A-7. Non-Architectural Performance Events for Intel Atom Processors
Event
Num.
Umask
Value Event Name Definition Description and Comment