Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 A-113
PERFORMANCE-MONITORING EVENTS
6AH See
Table
18-11
and
Table
18-12
BUS_TRANS_P
WR
Partial write bus
transaction.
This event counts partial write bus
transactions.
6BH See
Table
18-11
and
Table
18-12
BUS_TRANS_P Partial bus
transactions
This event counts all (read and write) partial
bus transactions.
6CH See
Table
18-11
and
Table
18-12
BUS_TRANS_IO IO bus
transactions
This event counts the number of completed
I/O bus transactions as a result of IN and OUT
instructions. The count does not include
memory mapped IO.
6DH See
Table
18-11
and
Table
18-12
BUS_TRANS_D
EF
Deferred bus
transactions
This event counts the number of deferred
transactions.
6EH See
Table
18-11
and
Table
18-12
BUS_TRANS_B
URST
Burst (full
cache-line) bus
transactions.
This event counts burst (full cache line)
transactions including:
- Burst reads
- RFOs
- Explicit writebacks
- Write combine lines
6FH See
Table
18-11
and
Table
18-12
BUS_TRANS_M
EM
Memory bus
transactions
This event counts all memory bus
transactions including:
- burst transactions
- partial reads and writes
- invalidate transactions
The BUS_TRANS_MEM count is the sum of
BUS_TRANS_BURST, BUS_TRANS_P and
BUS_TRANS_INVAL.
Table A-7. Non-Architectural Performance Events for Intel Atom Processors
Event
Num.
Umask
Value Event Name Definition Description and Comment