Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 18-51
DEBUGGING AND PERFORMANCE MONITORING
• Enable field (lowest 2 bits within each 4-bit control) — When bit 0 is set,
performance counting is enabled in the corresponding fixed-function
performance counter to increment while the target condition associated with the
architecture performance event occurred at ring 0. When bit 1 is set,
performance counting is enabled in the corresponding fixed-function
performance counter to increment while the target condition associated with the
architecture performance event occurred at ring greater than 0. Writing 0 to both
bits stops the performance counter. Writing a value of 11B enables the counter to
increment irrespective of privilege levels.
• PMI field (the fourth bit within each 4-bit control) — When set, the logical
processor generates an exception through its local APIC on overflow condition of
the respective fixed-function counter.
IA32_PERF_GLOBAL_CTRL MSR provides single-bit controls to enable counting of
each performance counter. Figure 18-15 shows the layout of
IA32_PERF_GLOBAL_CTRL. Each enable bit in IA32_PERF_GLOBAL_CTRL is AND’ed
with the enable bits for all privilege levels in the respective IA32_PERFEVTSELx or
IA32_PERF_FIXED_CTR_CTRL MSRs to start/stop the counting of respective
counters. Counting is enabled if the AND’ed results is true; counting is disabled when
the result is false.
The fixed-function performance counters supported by architectural performance
version 2 is listed in Table 18-17, the pairing between each fixed-function perfor-
mance counter to an architectural performance event is also shown.
IA32_PERF_GLOBAL_STATUS MSR provides single-bit status for software to query
the overflow condition of each performance counter. The MSR also provides addi-
tional status bit to indicate overflow conditions when counters are programmed for
precise-event-based sampling (PEBS). IA32_PERF_GLOBAL_STATUS MSR also
provides a sticky bit to indicate changes to the state of performance monitoring hard-
Figure 18-15. Layout of IA32_PERF_GLOBAL_CTRL MSR
IA32_FIXED_CTR2 enable
IA32_FIXED_CTR1 enable
IA32_FIXED_CTR0 enable
IA32_PMC1 enable
2
1
0
IA32_PMC0 enable
3132333435
Reserved
63