Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 A-149
PERFORMANCE-MONITORING EVENTS
Asserted two processor clock
cycles for partial writes and 4
processor clocks (usually in
consecutive bus clocks) for full
line writes.
1: DRDY_OWN Count when this processor reads
data from the bus - includes loads
and some PIC transactions.
Asserted two processor clock
cycles for partial reads and 4
processor clocks (usually in
consecutive bus clocks) for full
line reads.
Count DRDY events that we drive.
Count DRDY events sampled that
we own.
2: DRDY_OTHER Count when data is on the bus but
not being sampled by the
processor. It may or may not be
being driven by this processor.
Asserted two processor clock
cycles for partial transactions and
4 processor clocks (usually in
consecutive bus clocks) for full
line transactions.
3: DBSY_DRV Count when this processor
reserves the bus for use in the
next bus cycle in order to drive
data. Asserted for two processor
clock cycles for full line writes and
not at all for partial line writes.
May be asserted multiple times (in
consecutive bus clocks) if we stall
the bus waiting for a cache lock to
complete.
Table A-9. Performance Monitoring Events Supported by Intel NetBurst
Microarchitecture for Non-Retirement Counting (Contd.)
Event Name Event Parameters Parameter Value Description