Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

A-150 Vol. 3
PERFORMANCE-MONITORING EVENTS
4: DBSY_OWN Count when some agent reserves
the bus for use in the next bus
cycle to drive data that this
processor will sample.
Asserted for two processor clock
cycles for full line writes and not
at all for partial line writes. May be
asserted multiple times (all one
bus clock apart) if we stall the bus
for some reason.
5:DBSY_OTHER Count when some agent reserves
the bus for use in the next bus
cycle to drive data that this
processor will NOT sample. It may
or may not be being driven by this
processor.
Asserted two processor clock
cycles for partial transactions and
4 processor clocks (usually in
consecutive bus clocks) for full
line transactions.
CCCR Select 06H CCCR[15:13]
Event Specific
Notes
Specify edge trigger in the CCCR
MSR to avoid double counting.
DRDY_OWN and DRDY_OTHER are
mutually exclusive; similarly for
DBSY_OWN and DBSY_OTHER.
BSQ_allocation This event counts allocations in
the Bus Sequence Unit (BSQ)
according to the specified mask
bit encoding. The event mask bits
consist of four sub-groups:
•request type,
• request length
•memory type
• and sub-group consisting
mostly of independent bits
(bits 5, 6, 7, 8, 9, and 10)
Specify an encoding for each sub-
group.
Table A-9. Performance Monitoring Events Supported by Intel NetBurst
Microarchitecture for Non-Retirement Counting (Contd.)
Event Name Event Parameters Parameter Value Description