Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 18-55
DEBUGGING AND PERFORMANCE MONITORING
Each control block for a fixed-function performance counter provides a
AnyThread (bit position 2 + 4*N, N= 0, 1, etc.) bit. When set to 1, it enables
counting the associated event conditions (including matching the thread’s CPL
with the ENABLE setting of the corresponding control block of
IA32_PERF_FIXED_CTR_CTRL) occurring across all logical processors sharing a
processor core. When a AnyThread bit is 0 in IA32_PERF_FIXED_CTR_CTRL, the
corresponding fixed counter only increments the associated event conditions
occurring in the logical processor which programmed the
IA32_PERF_FIXED_CTR_CTRL MSR.
• The IA32_PERF_GLOBAL_CTRL, IA32_PERF_GLOBAL_STATUS,
IA32_PERF_GLOBAL_OVF_CTRL MSRs provide single-bit controls/status for each
general-purpose and fixed-function performance counter. Figure 18-20 shows
the layout of these MSR for N general-purpose performance counters (where N is
reported by CPUID.0AH:EAX[15:8] ) and three fixed-function counters.
Note: Intel Atom processor family supports two general-purpose performance
monitoring counters (i.e. N =2 in Figure 18-20), other processor families in Intel
64 architecture may support a different value of N in Figure 18-20. The number N
is reported by CPUID.0AH:EAX[15:8]. Intel Core i7 processor family supports
four general-purpose performance monitoring counters (i.e. N =4 in Figure
18-20)
Figure 18-19. Layout of IA32_FIXED_CTR_CTRL MSR Supporting Architectural
Performance Monitoring Version 3
Cntr2 — Controls for IA32_FIXED_CTR2
Cntr1 — Controls for IA32_FIXED_CTR1
PMI — Enable PMI on overflow on IA32_FIXED_CTR0
AnyThread — AnyThread for IA32_FIXED_CTR0
87 0
ENABLE — IA32_FIXED_CTR0. 0: disable; 1: OS; 2: User; 3: All ring levels
E
N
P
M
I
11 312 1
Reserved
63
2
E
N
E
N
495
P
P
M
M
I
I
A
N
Y
A
N
Y
A
N
Y