Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

A-186 Vol. 3
PERFORMANCE-MONITORING EVENTS
A.9 P6 FAMILY PROCESSOR PERFORMANCE-
MONITORING EVENTS
Table A-18 lists the events that can be counted with the performance-monitoring
counters and read with the RDPMC instruction for the P6 family processors. The unit
column gives the microarchitecture or bus unit that produces the event; the event
number column gives the hexadecimal number identifying the event; the mnemonic
event name column gives the name of the event; the unit mask column gives the unit
mask required (if any); the description column describes the event; and the
comments column gives additional information about the event.
All of these performance events are model specific for the P6 family processors and
are not available in this form in the Pentium 4 processors or the Pentium processors.
Some events (such as those added in later generations of the P6 family processors)
are only available in specific processors in the P6 family. All performance event
encodings not listed in Table A-18 are reserved and their use will result in undefined
counter results.
See the end of the table for notes related to certain entries in the table.
L2_LD 29H L2 data loads Mask[0] = 1 – count I state lines
Mask[1] = 1 – count S state
lines
Mask[2] = 1 – count E state
lines
Mask[3] = 1 – count M state
lines
Mask[5:4]:
00H – Excluding hardware-
prefetched lines
01H - Hardware-prefetched
lines only
02H/03H – All (HW-prefetched
lines and non HW --Prefetched
lines)
L2_LINES_IN 24H L2 lines
allocated
L2_LINES_OUT 26H L2 lines evicted
L2_M_LINES_OUT 27H Lw M-state lines
evicted
Table A-17. Performance Monitoring Events Modified on Intel
®
Pentium
®
M
Processors (Contd.)
Name Hex
Values
Descriptions