Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

A-204 Vol. 3
PERFORMANCE-MONITORING EVENTS
A.10 PENTIUM PROCESSOR PERFORMANCE-
MONITORING EVENTS
Table A-19 lists the events that can be counted with the performance-monitoring
counters for the Pentium processor. The Event Number column gives the hexadec-
imal code that identifies the event and that is entered in the ES0 or ES1 (event
select) fields of the CESR MSR. The Mnemonic Event Name column gives the name of
the event, and the Description and Comments columns give detailed descriptions of
the events. Most events can be counted with either counter 0 or counter 1; however,
some events can only be counted with only counter 0 or only counter 1 (as noted).
NOTE
The events in the table that are shaded are implemented only in the
Pentium processor with MMX technology.
Table A-19. Events That Can Be Counted with Pentium Processor
Performance-Monitoring Counters
Event
Num.
Mnemonic Event
Name Description Comments
00H DATA_READ Number of memory data
reads (internal data
cache hit and miss
combined)
Split cycle reads are counted
individually. Data Memory Reads that
are part of TLB miss processing are
not included. These events may
occur at a maximum of two per clock.
I/O is not included.
01H DATA_WRITE Number of memory data
writes (internal data
cache hit and miss
combined); I/O not
included
Split cycle writes are counted
individually. These events may occur
at a maximum of two per clock. I/O is
not included.
0H2 DATA_TLB_MISS Number of misses to the
data cache translation
look-aside buffer