Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 A-209
PERFORMANCE-MONITORING EVENTS
1BH STALL ON WRITE
TO AN E- OR M-
STATE LINE
Number of stalls on
writes to E- or M-state
lines
1CH LOCKED BUS CYCLE Number of locked bus
cycles that occur as the
result of the LOCK prefix
or LOCK instruction,
page-table updates, and
descriptor table updates
Only the read portion of the locked
read-modify-write is counted. Split
locked cycles (SCYC active) count as
two separate accesses. Cycles
restarted due to BOFF# are not re-
counted.
1DH I/O READ OR WRITE
CYCLE
Number of bus cycles
directed to I/O space
Misaligned I/O accesses will generate
two bus cycles. Bus cycles restarted
due to BOFF# are not re-counted.
1EH NONCACHEABLE_
MEMORY_READS
Number of
noncacheable
instruction or data
memory read bus cycles.
The count includes read
cycles caused by TLB
misses, but does not
include read cycles to
I/O space.
Cycles restarted due to BOFF# are
not re-counted.
1FH PIPELINE_AGI_
STALLS
Number of address
generation interlock
(AGI) stalls
An AGI occurring in both
the U- and V- pipelines
in the same clock signals
this event twice.
An AGI occurs when the instruction
in the execute stage of either of U-
or V-pipelines is writing to either the
index or base address register of an
instruction in the D2 (address
generation) stage of either the U- or
V- pipelines.
20H Reserved
21H Reserved
Table A-19. Events That Can Be Counted with Pentium Processor
Performance-Monitoring Counters (Contd.)
Event
Num.
Mnemonic Event
Name Description Comments