Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 18-61
DEBUGGING AND PERFORMANCE MONITORING
mance counters and associated counter control and status MSR becomes part of
architectural performance monitoring version 2 facilities (see also Section 18.13.2).
Non-architectural performance events in processors based on Intel Core microarchi-
tecture use event select values that are model-specific. Valid event mask (Umask)
bits are listed in Appendix A. The UMASK field may contain sub-fields identical to
those listed in Table 18-11, Table 18-12, Table 18-13, and Table 18-14. One or more
of these sub-fields may apply to specific events on an event-by-event basis. Details
are listed in Table A-6 in Appendix A, “Performance-Monitoring Events.”
In addition, the UMASK filed may also contain a sub-field that allows detection spec-
ificity related to snoop responses. Bits of the snoop response qualification sub-field
are defined in Table 18-15.
There are also non-architectural events that support qualification of different types of
snoop operation. The corresponding bit field for snoop type qualification are listed in
Table 18-16.
No more than one sub-field of MESI, snoop response, and snoop type qualification
sub-fields can be supported in a performance event.
NOTE
Software must write known values to the performance counters prior
to enabling the counters. The content of general-purpose counters
and fixed-function counters are undefined after INIT or RESET.
Table 18-15. Bus Snoop Qualification Definitions within a Non-Architectural Umask
IA32_PERFEVTSELx MSRs
Bit Position 11:8 Description
Bit 11 HITM response
Bit 10 Reserved
Bit 9 HIT response
Bit 8 CLEAN response
Table 18-16. Snoop Type Qualification Definitions within a Non-Architectural Umask
IA32_PERFEVTSELx MSRs
Bit Position 9:8 Description
Bit 9 CMP2I snoops
Bit 8 CMP2S snoops