Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

B-4 Vol. 3
MODEL-SPECIFIC REGISTERS (MSRS)
11 APIC Global Enable (R/W)
(MAXPHYWID - 1):12 APIC Base (R/W)
63: MAXPHYWID Reserved
3AH 58 IA32_FEATURE_CONTROL Control Features in Intel
64 Processor. (R/W)
If CPUID.01H:
ECX[bit 5 or bit 6]
= 1
0 Lock bit (R/WO): (1 = locked).
When set, locks this MSR
from being written, writes
to this bit will result in GP(0).
Note: Once the Lock bit is
set, the contents of this
register cannot be modified.
Therefore the lock bit must
be set after configuring
support
for Intel Virtualization
Technology and prior to
transferring control to an
option ROM or the OS.
Hence, once the Lock bit is
set, the entire
IA32_FEATURE_CONTROL_
MSR contents are preserved
across RESET when
PWRGOOD is not deasserted.
If
CPUID.01H:ECX[b
it 5 or bit 6] = 1
1 Enable VMX inside SMX
operation (R/WL): This bit
enables a system executive
to use VMX in conjunction
with SMX to support Intel®
Trusted Execution
Technology.
BIOS must set this bit only
when the CPUID function 1
returns VMX feature flag
and SMX feature flag set
(ECX bits 5 and 6
respectively).
If
CPUID.01H:ECX[b
it 5 and bit 6] are
set to 1
Table B-2. IA-32 Architectural MSRs (Contd.)
Register Address Architectural MSR Name
and bit fields
(Former MSR Name) MSR/Bit Description
Introduced as
Architectural
MSR
Hex Decimal