Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

B-6 Vol. 3
MODEL-SPECIFIC REGISTERS (MSRS)
8BH 139 IA32_BIOS_SIGN_ID
(BIOS_SIGN/BBL_CR
_D3)
BIOS Update Signature (RO)
Returns the microcode
update signature following
the execution of CPUID.01H.
A processor may prevent
writing to this MSR when
loading guest states on VM
entries or saving guest
states on VM exits.
06_01H
31:0 Reserved
63:32 It is recommended that this
field be pre-loaded with 0
prior to executing CPUID.
If the field remains 0
following the execution of
CPUID; this indicates that no
microcode update is loaded.
Any non-zero value is the
microcode update signature.
9BH 155 IA32_SMM_MONITOR_CTL SMM Monitor Configuration
(R/W)
If CPUID.01H:
ECX[bit 5 or bit 6]
= 1
0Valid (R/W)
11:1 Reserved
31:12 MSEG Base (R/W)
63:32 Reserved
C1H 193 IA32_PMC0 (PERFCTR0) General Performance
Counter 0 (R/W)
If CPUID.0AH:
EAX[15:8] > 0
C2H 194 IA32_PMC1 (PERFCTR1) General Performance
Counter 1 (R/W)
If CPUID.0AH:
EAX[15:8] > 1
C3H 195 IA32_PMC2 General Performance
Counter 2 (R/W)
If CPUID.0AH:
EAX[15:8] > 2
C4H 196 IA32_PMC3 General Performance
Counter 3 (R/W)
If CPUID.0AH:
EAX[15:8] > 3
Table B-2. IA-32 Architectural MSRs (Contd.)
Register Address Architectural MSR Name
and bit fields
(Former MSR Name) MSR/Bit Description
Introduced as
Architectural
MSR
Hex Decimal