Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 B-9
MODEL-SPECIFIC REGISTERS (MSRS)
7:0 Event Select: Selects a
performance event logic unit
15:8 UMask: Qualifies the
microarchitectural condition
to detect on the selected
event logic.
16 USR: Counts while in
privilege level is not ring 0.
17 OS: Counts while in privilege
level is ring 0.
18 Edge: Enables edge
detection if set
19 PC: enables pin control
20 INT: enables interrupt on
counter overflow
21 Reserved
22 EN: enables the
corresponding performance
counter to commence
counting when this bit is set
23 INV: invert the CMASK
31:24 CMASK: When CMASK is not
zero, the corresponding
performance counter
increments each cycle if the
event count is greater than
or equal to the CMASK.
63:32 Reserved
187H 391 IA32_PERFEVTSEL1
(PERFEVTSEL1)
Performance Event Select
Register 1 (R/W)
06_0EH
188H 392 IA32_PERFEVTSEL2 Performance Event Select
Register 2 (R/W)
If CPUID.0AH:
EAX[15:8] > 2
189H 393 IA32_PERFEVTSEL3 Performance Event Select
Register 3 (R/W)
If CPUID.0AH:
EAX[15:8] > 3
Table B-2. IA-32 Architectural MSRs (Contd.)
Register Address Architectural MSR Name
and bit fields
(Former MSR Name) MSR/Bit Description
Introduced as
Architectural
MSR
Hex Decimal