Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 18-63
DEBUGGING AND PERFORMANCE MONITORING
• PMI field (fourth bit in each 4-bit control) — When set, the logical processor
generates an exception through its local APIC on overflow condition of the
respective fixed-function counter.
18.15.2 Global Counter Control Facilities
Processors based on Intel Core microarchitecture provides simplified performance
counter control that simplifies the most frequent operations in programming perfor-
mance events, i.e. enabling/disabling event counting and checking the status of
counter overflows. This is done by the following three MSRs:
• MSR_PERF_GLOBAL_CTRL enables/disables event counting for all or any
combination of fixed-function PMCs (MSR_PERF_FIXED_CTRx) or general-
purpose PMCs via a single WRMSR.
• MSR_PERF_GLOBAL_STATUS allows software to query counter overflow
conditions on any combination of fixed-function PMCs (MSR_PERF_FIXED_CTRx)
or general-purpose PMCs via a single RDMSR.
• MSR_PERF_GLOBAL_OVF_CTRL allows software to clear counter overflow
conditions on any combination of fixed-function PMCs (MSR_PERF_FIXED_CTRx)
or general-purpose PMCs via a single WRMSR.
MSR_PERF_GLOBAL_CTRL MSR provides single-bit controls to enable counting in
each performance counter (see Figure 18-22). Each enable bit in
MSR_PERF_GLOBAL_CTRL is AND’ed with the enable bits for all privilege levels in the
respective IA32_PERFEVTSELx or MSR_PERF_FIXED_CTR_CTRL MSRs to start/stop
the counting of respective counters. Counting is enabled if the AND’ed results is true;
counting is disabled when the result is false.
Figure 18-21. Layout of MSR_PERF_FIXED_CTR_CTRL MSR
Cntr2 — Controls for MSR_PERF_FIXED_CTR2
Cntr1 — Controls for MSR_PERF_FIXED_CTR1
PMI — Enable PMI on overflow
Cntr0 — Controls for MSR_PERF_FIXED_CTR0
87 0
ENABLE — 0: disable; 1: OS; 2: User; 3: All ring levels
E
N
P
M
I
11 312 1
Reserved
63
2
E
N
E
N
495
P
P
M
M
I
I