Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

18-64 Vol. 3
DEBUGGING AND PERFORMANCE MONITORING
MSR_PERF_GLOBAL_STATUS MSR provides single-bit status used by software to
query the overflow condition of each performance counter. The MSR also provides
additional status bit to indicate overflow conditions when counters are programmed
for precise-event-based sampling (PEBS). The MSR_PERF_GLOBAL_STATUS MSR
also provides a ‘sticky bit’ to indicate changes to the state of performance monitoring
hardware (see Figure 18-23). A value of 1 in bits 34:32, 1, 0 indicates an overflow
condition has occurred in the associated counter.
When a performance counter is configured for PEBS, an overflow condition in the
counter generates a performance-monitoring interrupt this signals a PEBS event. On
a PEBS event, the processor stores data records in the buffer area (see Section
18.18.5), clears the counter overflow status, and sets the OvfBuffer bit in
MSR_PERF_GLOBAL_STATUS.
Figure 18-22. Layout of MSR_PERF_GLOBAL_CTRL MSR
Figure 18-23. Layout of MSR_PERF_GLOBAL_STATUS MSR
FIXED_CTR2 enable
FIXED_CTR1 enable
FIXED_CTR0 enable
PMC1 enable
2
1
0
PMC0 enable
3132333435
Reserved
63
62
FIXED_CTR2 Overflow
FIXED_CTR1 Overflow
FIXED_CTR0 Overflow
PMC1 Overflow
21
0
PMC0 Overflow
3132333435
Reserved
63
CondChgd
OvfBuffer