Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

B-44 Vol. 3
MODEL-SPECIFIC REGISTERS (MSRS)
9 Hardware Prefetcher Disable. (R/W)
When set, disables the hardware prefetcher
operation on streams of data. When clear
(default), enables the prefetch queue.
Disabling of the hardware prefetcher may
impact processor performance.
10 Shared FERR# Multiplexing Enable. (R/W)
1 = FERR# asserted by the processor to
indicate a pending break event within
the processor
0 = Indicates compatible FERR# signaling
behavior
This bit must be set to 1 to support XAPIC
interrupt model usage.
11 Shared Branch Trace Storage Unavailable. (RO) see
Table B-2
12 Shared Precise Event Based Sampling Unavailable.
(RO) see Table B-2
13 Shared TM2 Enable. (R/W)
When this bit is set (1) and the thermal sensor
indicates that the die temperature is at the
pre-determined threshold, the Thermal
Monitor 2 mechanism is engaged. TM2 will
reduce the bus to core ratio and voltage
according to the value last written to
MSR_THERM2_CTL bits 15:0.
When this bit is clear (0, default), the
processor does not change the VID signals or
the bus to core ratio when the processor
enters a thermally managed state.
The BIOS must enable this feature if the TM2
feature flag (CPUID.1:ECX[8]) is set; if the TM2
feature flag is not set, this feature is not
supported and BIOS must not alter the
contents of the TM2 bit location.
The processor is operating out of specification
if both this bit and the TM1 bit are set to 0.
Table B-3. MSRs in Processors Based on Intel Core Microarchitecture (Contd.)
Register
Address Register Name
Shared/
Unique Bit Description
Hex Dec