Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 B-45
MODEL-SPECIFIC REGISTERS (MSRS)
15:14 Reserved.
16 Shared Enhanced Intel SpeedStep Technology
Enable. (R/W) see Table B-2
18 Shared ENABLE MONITOR FSM. (R/W) see Table B-2
19 Shared Adjacent Cache Line Prefetch Disable.
(R/W)
When set to 1, the processor fetches the
cache line that contains data currently
required by the processor. When set to 0, the
processor fetches cache lines that comprise a
cache line pair (128 bytes).
Single processor platforms should not set this
bit. Server platforms should set or clear this
bit based on platform performance observed
in validation and testing.
BIOS may contain a setup option that controls
the setting of this bit.
20 Shared Enhanced Intel SpeedStep Technology
Select Lock. (R/WO)
When set, this bit causes the following bits to
become read-only:
• Enhanced Intel SpeedStep Technology
Select Lock (this bit),
• Enhanced Intel SpeedStep Technology
Enable bit.
The bit must be set before an Enhanced Intel
SpeedStep Technology transition is requested.
This bit is cleared on reset.
21 Reserved.
22 Shared Limit CPUID Maxval. (R/W) see Table B-2
23 Shared xTPR Message Disable. (R/W) see Table B-2
33:24 Reserved.
34 Unique XD Bit Disable. (R/W) see Table B-2
36:35 Reserved.
Table B-3. MSRs in Processors Based on Intel Core Microarchitecture (Contd.)
Register
Address Register Name
Shared/
Unique Bit Description
Hex Dec