Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 18-67
DEBUGGING AND PERFORMANCE MONITORING
18.15.4.1 Setting up the PEBS Buffer
For processors based on Intel Core microarchitecture, PEBS is available using
IA32_PMC0 only. Use the following procedure to set up the processor and
IA32_PMC0 counter for PEBS:
1. Set up the precise event buffering facilities. Place values in the precise event
buffer base, precise event index, precise event absolute maximum, precise event
interrupt threshold, and precise event counter reset fields of the DS buffer
management area. In processors based on Intel Core microarchitecture, PEBS
records consist of 64-bit address entries. See Figure 18-41 to set up the precise
event records buffer in memory.
2. Enable PEBS. Set the Enable PEBS on PMC0 flag (bit 0) in IA32_PEBS_ENABLE
MSR.
3. Set up the IA32_PMC0 performance counter and IA32_PERFEVTSEL0 for an
event listed in Table 18-19.
18.15.4.2 PEBS Record Format
The PEBS record format may be extended across different processor implementa-
tions. The IA32_PERF_CAPABILITES MSR defines a mechanism for software to
handle the evolution of PEBS record format in processors that support architectural
performance monitoring with version id equals 2 or higher. The bit fields of
IA32_PERF_CAPABILITES are defined in Table B-2 of Appendix B, “Model-Specific
Registers (MSRs)”. The relevant bit fields that governs PEBS are:
• PEBSTrap [bit 6]: When set, PEBS recording is trap-like. After the PEBS-enabled
counter has overflowed, PEBS record is recorded for the next PEBS-able event at
the completion of the sampled instruction causing the PEBS event. When clear,
PEBS recording is fault-like. The PEBS record is recorded before the sampled
instruction causing the PEBS event.
• PEBSSaveArchRegs [bit 7]: When set, PEBS will save architectural register and
state information according to the encoded value of the PEBSRecordFormat field.
On processors based on Intel Core microarchitecture, this bit is always 1
• PEBSRecordFormat [bits 11:8]: Valid encodings are:
— 0000B: Only general-purpose registers, instruction pointer and RFLAGS
registers are saved in each PEBS record (seeSection 18.18.8).
18.15.4.3 Writing a PEBS Interrupt Service Routine
The PEBS facilities share the same interrupt vector and interrupt service routine
(called the DS ISR) with the non-precise event-based sampling and BTS facilities. To
handle PEBS interrupts, PEBS handler code must be included in the DS ISR. See
Section 18.5.3.2, “Debug Store (DS) Mechanism,” for guidelines when writing the DS
ISR.