Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 B-63
MODEL-SPECIFIC REGISTERS (MSRS)
12 Shared Precise Event Based Sampling Unavailable.
(RO) see Table B-2
13 Shared TM2 Enable. (R/W)
When this bit is set (1) and the thermal sensor
indicates that the die temperature is at the
pre-determined threshold, the Thermal
Monitor 2 mechanism is engaged. TM2 will
reduce the bus to core ratio and voltage
according to the value last written to
MSR_THERM2_CTL bits 15:0.
When this bit is clear (0, default), the
processor does not change the VID signals or
the bus to core ratio when the processor
enters a thermally managed state.
The BIOS must enable this feature if the TM2
feature flag (CPUID.1:ECX[8]) is set; if the TM2
feature flag is not set, this feature is not
supported and BIOS must not alter the
contents of the TM2 bit location.
The processor is operating out of specification
if both this bit and the TM1 bit are set to 0.
15:14 Reserved.
16 Shared Enhanced Intel SpeedStep Technology
Enable. (R/W) see Table B-2
18 Shared ENABLE MONITOR FSM. (R/W) see Table B-2
19 Reserved.
20 Shared Enhanced Intel SpeedStep Technology
Select Lock. (R/WO)
When set, this bit causes the following bits to
become read-only:
• Enhanced Intel SpeedStep Technology
Select Lock (this bit),
• Enhanced Intel SpeedStep Technology
Enable bit.
The bit must be set before an Enhanced Intel
SpeedStep Technology transition is requested.
This bit is cleared on reset.
Table B-4. MSRs in Intel Atom Processor Family
Register
Address Register Name
Shared/
Unique Bit Description
Hex Dec