Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 B-65
MODEL-SPECIFIC REGISTERS (MSRS)
38EH 910 IA32_PERF_
GLOBAL_STAUS
Unique see Table B-2. See Section 18.15.2, “Global
Counter Control Facilities.”
38FH 911 IA32_PERF_
GLOBAL_CTRL
Unique see Table B-2. See Section 18.15.2, “Global
Counter Control Facilities.”
390H 912 IA32_PERF_
GLOBAL_OVF_
CTRL
Unique see Table B-2. See Section 18.15.2, “Global
Counter Control Facilities.”
3F1H 1009 IA32_PEBS_
ENABLE
Unique see Table B-2. See Section 18.15.4, “Precise
Event Based Sampling (PEBS).”
0 Enable PEBS on IA32_PMC0. (R/W)
400H 1024 IA32_MC0_CTL Shared See Section 14.3.2.1, “IA32_MCi_CTL MSRs.”
401H 1025 IA32_MC0_
STATUS
Shared See Section 14.3.2.2, “IA32_MCi_STATUS
MSRS.”
402H 1026 IA32_MC0_ADDR Shared See Section 14.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC0_ADDR register is either not
implemented or contains no address if the
ADDRV flag in the IA32_MC0_STATUS register
is clear.
When not implemented in the processor, all
reads and writes to this MSR will cause a
general-protection exception.
404H 1028 IA32_MC1_CTL Shared See Section 14.3.2.1, “IA32_MCi_CTL MSRs.”
405H 1029 IA32_MC1_
STATUS
Shared See Section 14.3.2.2, “IA32_MCi_STATUS
MSRS.”
408H 1032 IA32_MC2_CTL Shared See Section 14.3.2.1, “IA32_MCi_CTL MSRs.”
409H 1033 IA32_MC2_
STATUS
Shared See Section 14.3.2.2, “IA32_MCi_STATUS
MSRS.”
40AH 1034 IA32_MC2_ADDR Shared See Section 14.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC2_ADDR register is either not
implemented or contains no address if the
ADDRV flag in the IA32_MC2_STATUS register
is clear.
When not implemented in the processor, all
reads and writes to this MSR will cause a
general-protection exception.
Table B-4. MSRs in Intel Atom Processor Family
Register
Address Register Name
Shared/
Unique Bit Description
Hex Dec