Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

B-68 Vol. 3
MODEL-SPECIFIC REGISTERS (MSRS)
B.4 MSRS IN THE INTEL
®
MICROARCHITECTURE
(NEHALEM)
Table B-5 lists model-specific registers (MSRs) for Intel microarchitecture (Nehalem).
These include Intel Core i7 processor family. Architectural MSR addresses are also
included in Table B-5. These processors have a CPUID signature with
DisplayFamily_DisplayModel of 06_1AH, see Table B-1.
The column “Scope” represents the package/core/thread scope of individual bit field
of an MSR. “Thread” means this bit field must be programmed on each logical
processor independently. “Core” means the bit field must be programmed on each
processor core independently, logical processors in the same core will be affected by
change of this bit on the other logical processor in the same core. “Package“ means
the bit field must be programmed once for each physical package. Change of a bit
filed with a package scope will affect all logical processors in that physical package.
Table B-5. MSRs in Processors Based on Intel Microarchitecture (Nehalem)
Register
Address Register Name
Scope
Bit Description
Hex Dec
0H 0 IA32_P5_MC_
ADDR
Thread See Appendix B.9, “MSRs in Pentium
Processors.”
1H 1 IA32_P5_MC_
TYPE
Thread See Appendix B.9, “MSRs in Pentium
Processors.”
6H 6 IA32_MONITOR_
FILTER_SIZE
Thread See Section 7.11.5, “Monitor/Mwait Address
Range Determination.” andTable B-2
10H 16 IA32_TIME_
STAMP_COUNTER
Thread See Section 18.11, “Time-Stamp Counter.” and
see Table B-2
17H 23 IA32_PLATFORM_I
D
Package Platform ID. (R)
See Table B-2.
17H 23 MSR_PLATFORM_I
D
Package Model Specific Platform ID. (R)
49:0 Reserved.
52:50 See Table B-2.
63:53 Reserved.
1BH 27 IA32_APIC_BASE Thread See Section 9.4.4, “Local APIC Status and
Location.” and Table B-2
3AH 58 IA32_FEATURE_
CONTROL
Thread Control Features in Intel 64Processor.
(R/W).
see Table B-2