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Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

ManualsBrandsIntel ManualsOtherIntel Pentium 4 Processor 2.80 GHz, 512K Cache, 533 MHz FSB
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Table Of Contents
B-76 Vol. 3
MODEL-SPECIFIC REGISTERS (MSRS)
391H 913 MSR_UNCORE_PE
RF_GLOBAL_CTRL
Package See Section 18.17.2.1, “Uncore Performance
Monitoring Management Facility.”
392H 914 MSR_UNCORE_PE
RF_GLOBAL_STAT
US
Package See Section 18.17.2.1, “Uncore Performance
Monitoring Management Facility.”
393H 915 MSR_UNCORE_PE
RF_GLOBAL_OVF_
CTRL
Package See Section 18.17.2.1, “Uncore Performance
Monitoring Management Facility.”
394H 916 MSR_UNCORE_FIX
ED_CTR0
Package See Section 18.17.2.1, “Uncore Performance
Monitoring Management Facility.”
395H 917 MSR_UNCORE_FIX
ED_CTR_CTRL
Package See Section 18.17.2.1, “Uncore Performance
Monitoring Management Facility.”
396H 918 MSR_UNCORE_AD
DR_OPCODE_MAT
CH
Package See Section 18.17.2.3, “Uncore
Address/Opcode Match MSR.”
3B0H 944 MSR_UNCORE_PE
RFEVTSEL0
Package See Section 18.17.2.2, “Uncore Performance
Event Configuration Facility.”
3B1H 945 MSR_UNCORE_PE
RFEVTSEL1
Package See Section 18.17.2.2, “Uncore Performance
Event Configuration Facility.”
3B2H 946 MSR_UNCORE_PE
RFEVTSEL2
Package See Section 18.17.2.2, “Uncore Performance
Event Configuration Facility.”
3B3H 947 MSR_UNCORE_PE
RFEVTSEL3
Package See Section 18.17.2.2, “Uncore Performance
Event Configuration Facility.”
3B4H 948 MSR_UNCORE_PE
RFEVTSEL4
Package See Section 18.17.2.2, “Uncore Performance
Event Configuration Facility.”
3B5H 949 MSR_UNCORE_PE
RFEVTSEL5
Package See Section 18.17.2.2, “Uncore Performance
Event Configuration Facility.”
3B6H 950 MSR_UNCORE_PE
RFEVTSEL6
Package See Section 18.17.2.2, “Uncore Performance
Event Configuration Facility.”
3B7H 951 MSR_UNCORE_PE
RFEVTSEL7
Package See Section 18.17.2.2, “Uncore Performance
Event Configuration Facility.”
3C0H 960 MSR_UNCORE_PM
C0
Package See Section 18.17.2.2, “Uncore Performance
Event Configuration Facility.”
3C1H 961 MSR_UNCORE_PM
C1
Package See Section 18.17.2.2, “Uncore Performance
Event Configuration Facility.”
Table B-5. MSRs in Processors Based on Intel Microarchitecture (Contd.)(Nehalem)
Register
Address Register Name
Scope
Bit Description
Hex Dec