Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 B-77
MODEL-SPECIFIC REGISTERS (MSRS)
3C2H 962 MSR_UNCORE_PM
C2
Package See Section 18.17.2.2, “Uncore Performance
Event Configuration Facility.”
3C3H 963 MSR_UNCORE_PM
C3
Package See Section 18.17.2.2, “Uncore Performance
Event Configuration Facility.”
3C4H 964 MSR_UNCORE_PM
C4
Package See Section 18.17.2.2, “Uncore Performance
Event Configuration Facility.”
3C5H 965 MSR_UNCORE_PM
C5
Package See Section 18.17.2.2, “Uncore Performance
Event Configuration Facility.”
3C6H 966 MSR_UNCORE_PM
C6
Package See Section 18.17.2.2, “Uncore Performance
Event Configuration Facility.”
3C7H 967 MSR_UNCORE_PM
C7
Package See Section 18.17.2.2, “Uncore Performance
Event Configuration Facility.”
3F1H 1009 IA32_PEBS_
ENABLE
Thread see See Section 18.17.1.1, “Precise Event
Based Sampling (PEBS).”
0 Enable PEBS on IA32_PMC0. (R/W)
1 Enable PEBS on IA32_PMC1. (R/W)
2 Enable PEBS on IA32_PMC2. (R/W)
3 Enable PEBS on IA32_PMC3. (R/W)
31:4 Reserved
32 Enable Load Latency on IA32_PMC0. (R/W)
33 Enable Load Latency on IA32_PMC1. (R/W)
34 Enable Load Latency on IA32_PMC2. (R/W)
35 Enable Load Latency on IA32_PMC3. (R/W)
63:36 Reserved
3F6H 1014 MSR_PEBS_
LD_LAT
Thread see See Section 18.17.1.2, “Load Latency
Performance Monitoring Facility.”
15:0 Minimum threshold latency value of tagged
load operation that will be counted. (R/W)
63:36 Reserved
3F8H 1016 MSR_PKG_C3_RES
IDENCY
Package
Table B-5. MSRs in Processors Based on Intel Microarchitecture (Contd.)(Nehalem)
Register
Address Register Name
Scope
Bit Description
Hex Dec