Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 B-89
MODEL-SPECIFIC REGISTERS (MSRS)
B.5 MSRS IN THE PENTIUM
®
4 AND INTEL
®
XEON
®
PROCESSORS
Table B-6 lists MSRs (architectural and model-specific) that are defined across
processor generations based on Intel NetBurst microarchitecture. The processor can
be identified by its CPUID signatures of DisplayFamily encoding of 0FH, see
Table B-1.
• MSRs with an “IA32_” prefix are designated as “architectural.” This means that
the functions of these MSRs and their addresses remain the same for succeeding
families of IA-32 processors.
• MSRs with an “MSR_” prefix are model specific with respect to address function-
alities. The column “Model Availability” lists the model encoding value(s) within
the Pentium 4 and Intel Xeon processor family at the specified register address.
The model encoding value of a processor can be queried using CPUID. See
“CPUID—CPU Identification” in Chapter 3 of the Intel® 64 and IA-32 Architec-
tures Software Developer’s Manual, Volume 2A.
Table B-6. MSRs in the Pentium 4 and Intel Xeon Processors
Register
Address
Register Name
Fields and Flags
Model
Avail-
ability
Shared/
Unique
1
Bit Description
Hex Dec
0H 0 IA32_P5_MC_ADDR 0, 1, 2,
3, 4, 6
Shared See Appendix B.9, “MSRs in
Pentium Processors.”
1H 1 IA32_P5_MC_TYPE 0, 1, 2,
3, 4, 6
Shared See Appendix B.9, “MSRs in
Pentium Processors.”
6H 6 IA32_MONITOR_
FILTER_LINE_SIZE
3, 4, 6 Shared See Section 7.11.5,
“Monitor/Mwait Address Range
Determination.”
10H 16 IA32_TIME_STAMP_
COUNTER
0, 1, 2,
3, 4, 6
Unique Time Stamp Counter.
see Table B-2
On earlier processors, only the
lower 32 bits are writable. On any
write to the lower 32 bits, the
upper 32 bits are cleared. For
processor family 0FH, models 3
and 4: all 64 bits are writable.