Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

B-90 Vol. 3
MODEL-SPECIFIC REGISTERS (MSRS)
17H 23 IA32_PLATFORM_ID 0, 1, 2,
3, 4, 6
Shared Platform ID. (R). see Table B-2
The operating system can use this
MSR to determine “slot”
information for the processor and
the proper microcode update to
load.
1BH 27 IA32_APIC_BASE 0, 1, 2,
3, 4, 6
Unique APIC Location and Status. (R/W)
see Table B-2. See Section 9.4.4,
“Local APIC Status and Location.”
2AH 42 MSR_EBC_HARD_
POWERON
0, 1, 2,
3, 4, 6
Shared Processor Hard Power-On
Configuration.
(R/W) Enables and disables
processor features; (R) indicates
current processor configuration.
0 Output Tri-state Enabled. (R)
Indicates whether tri-state output
is enabled (1) or disabled (0) as set
by the strapping of SMI#. The
value in this bit is written on the
deassertion of RESET#; the bit is
set to 1 when the address bus
signal is asserted.
1 Execute BIST. (R)
Indicates whether the execution
of the BIST is enabled (1) or
disabled (0) as set by the
strapping of INIT#. The value in
this bit is written on the
deassertion of RESET#; the bit is
set to 1 when the address bus
signal is asserted.
Table B-6. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)
Register
Address
Register Name
Fields and Flags
Model
Avail-
ability
Shared/
Unique
1
Bit Description
Hex Dec