Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

18-70 Vol. 3
DEBUGGING AND PERFORMANCE MONITORING
Valid event mask (Umask) bits are listed in Appendix A. The UMASK field may contain
sub-fields that provide the same qualifying actions like those listed in Table 18-11,
Table 18-12, Table 18-13, and Table 18-14. One or more of these sub-fields may
apply to specific events on an event-by-event basis. Details are listed in Table A-7 in
Appendix A, “Performance-Monitoring Events.” Precise Event Based Monitoring is
supported using IA32_PMC0.
18.17 PERFORMANCE MONITORING FOR PROCESSORS
BASED ON INTEL
®
MICROARCHITECTURE (NEHALEM)
Intel Core i7 processor family supports architectural performance monitoring capa-
bility with version ID 3 (see Section 18.13.2.2) and a host of non-architectural moni-
toring capabilities. The Intel Core i7 processor family is based on Intel®
microarchitecture (Nehalem), and provides four general-purpose performance
counters (IA32_PMC0, IA32_PMC1, IA32_PMC2, IA32_PMC3) and three fixed-func-
tion performance counters (IA32_FIXED_CTR0, IA32_FIXED_CTR1,
IA32_FIXED_CTR2) in the processor core.
Non-architectural performance monitoring in Intel Core i7 processor family uses the
IA32_PERFEVTSELx MSR to configure a set of non-architecture performance moni-
toring events to be counted by the corresponding general-purpose performance
counter. The list of non-architectural performance monitoring events is listed in Table
A-7. Non-architectural performance monitoring events fall into two broad categories:
• Performance monitoring events in the processor core: These include many
events that are similar to performance monitoring events available to processor
based on Intel Core microarchitecture. Additionally, there are several enhance-
ments in the performance monitoring capability for detecting microarchitectural
conditions in the processor core or in the interaction of the processor core to the
off-core sub-systems in the physical processor package. The off-core sub-
systems in the physical processor package is loosely referred to as “uncore“.
• Performance monitoring events in the uncore: The uncore sub-system is shared
by more than one processor cores in the physical processor package. It provides
additional performance monitoring facility outside of IA32_PMCx and
performance monitoring events that are specific to the uncore sub-system.
Architectural and non-architectural performance monitoring events in Intel Core i7
processor family support thread qualification using bit 21 of IA32_PERFEVTSELx
MSR.
The bit fields within each IA32_PERFEVTSELx MSR are defined in Figure 18-18 and
described in Section 18.13.1.1 and Section 18.13.2.2.