Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

B-94 Vol. 3
MODEL-SPECIFIC REGISTERS (MSRS)
18:16 Scalable Bus Speed. (R/W)
Indicates the intended scalable
bus speed:
Encoding Scalable Bus Speed
000B 100 MHz (Model 2)
000B 266 MHz (Model 3 or 4)
001B 133 MHz
010B 200 MHz
011B 166 MHz
100B 333 MHz (Model 6)
133.33 MHz should be utilized if
performing calculation with
System Bus Speed when encoding
is 001B.
166.67 MHz should be utilized if
performing calculation with
System Bus Speed when encoding
is 011B.
266.67 MHz should be utilized if
performing calculation with
System Bus Speed when encoding
is 000B and model encoding = 3
or 4.
333.33 MHz should be utilized if
performing calculation with
System Bus Speed when encoding
is 100B and model encoding = 6.
All other values are reserved.
23:19 Reserved
31:24 Core Clock Frequency to System
Bus Frequency Ratio. (R)
The processor core clock
frequency to system bus
frequency ratio observed at the
de-assertion of the reset pin.
63:25 Reserved.
Table B-6. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)
Register
Address
Register Name
Fields and Flags
Model
Avail-
ability
Shared/
Unique
1
Bit Description
Hex Dec