Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

B-96 Vol. 3
MODEL-SPECIFIC REGISTERS (MSRS)
174H 372 IA32_SYSENTER_CS 0, 1, 2,
3, 4, 6
Unique CS register target for CPL 0
code. (R/W). see Table B-2
See Section 4.8.7, “Performing
Fast Calls to System Procedures
with the SYSENTER and SYSEXIT
Instructions.”
175H 373 IA32_SYSENTER_ESP 0, 1, 2,
3, 4, 6
Unique Stack pointer for CPL 0 stack.
(R/W). see Table B-2
See Section 4.8.7, “Performing
Fast Calls to System Procedures
with the SYSENTER and SYSEXIT
Instructions.”
176H 374 IA32_SYSENTER_EIP 0, 1, 2,
3, 4, 6
Unique CPL 0 code entry point. (R/W).
see Table B-2. See Section 4.8.7,
“Performing Fast Calls to System
Procedures with the SYSENTER
and SYSEXIT Instructions.”
179H 377 IA32_MCG_CAP 0, 1, 2,
3, 4, 6
Unique Machine Check Capabilities. (R)
see Table B-2. See Section
14.3.1.1, “IA32_MCG_CAP MSR.”
17AH 378 IA32_MCG_STATUS 0, 1, 2,
3, 4, 6
Unique Machine Check Status. (R). see
Table B-2. See Section 14.3.1.2,
“IA32_MCG_STATUS MSR.”
17BH 379 IA32_MCG_CTL Machine Check Feature Enable.
(R/W). see Table B-2
See Section 14.3.1.3,
“IA32_MCG_CTL MSR.”
180H 384 MSR_MCG_RAX 0, 1, 2,
3, 4, 6
Unique Machine Check EAX/RAX Save
State.
See Section 14.3.2.6, “IA32_MCG
Extended Machine Check State
MSRs.”
63:0 Contains register state at time of
machine check error. When in non-
64-bit modes at the time of the
error, bits 63-32 do not contain
valid data.
Table B-6. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)
Register
Address
Register Name
Fields and Flags
Model
Avail-
ability
Shared/
Unique
1
Bit Description
Hex Dec