Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

18-72 Vol. 3
DEBUGGING AND PERFORMANCE MONITORING
Upon occurrence of the next PEBS event, the PEBS hardware triggers an assist and
causes a PEBS record to be written. The format of the PEBS record is indicated by the
bit field IA32_PERF_CAPABILITIES[11:8] (see Figure 18-47).
The behavior of PEBS assists is reported by IA32_PERF_CAPABILITIES[6] (see
Figure 18-47). The return instruction pointer (RIP) reported in the PEBS record will
point to the instruction after (+1) the instruction that causes the PEBS assist. The
machine state reported in the PEBS record is the machine state after the instruction
that causes the PEBS assist is retired. For instance, if the instructions:
mov eax, [eax] ; causes PEBS assist
nop
are executed, the PEBS record will report the address of the nop, and the value of
EAX in the PEBS record will show the value read from memory, not the target address
of the read operation.
The PEBS record format is shown in Table 18-21, and each field in the PEBS record is
64 bits long. The PEBS record format, along with debug/store area storage format,
does not change regardless of IA-32e mode is active or not.
CPUID.01H:ECX.DTES64[bit 2] reports the processor’s support for 64-bit
debug/store area storage format is invariant to IA-32e mode.
Figure 18-25. Layout of IA32_PEBS_ENABLE MSR
Table 18-21. PEBS Record Format for Intel Core i7 Processor Family
Byte Offset Field Byte Offset Field
0x0 R/EFLAGS 0x58 R9
LL_EN_PMC3 (R/W)
LL_EN_PMC2 (R/W)
87 0
LL_EN_PMC1 (R/W)
32
3
33
1
Reserved
63
24
31
5
6
343536
PEBS_EN_PMC3 (R/W)
PEBS_EN_PMC2 (R/W)
PEBS_EN_PMC1 (R/W)
PEBS_EN_PMC0 (R/W)
LL_EN_PMC0 (R/W)
RESET Value — 0x00000000_00000000