Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

B-118 Vol. 3
MODEL-SPECIFIC REGISTERS (MSRS)
3CAH 970 MSR_ALF_ESCR0 0, 1, 2,
3, 4, 6
Shared See Section 18.18.1, “ESCR MSRs.”
3CBH 971 MSR_ALF_ESCR1 0, 1, 2,
3, 4, 6
Shared See Section 18.18.1, “ESCR MSRs.”
3CCH 972 MSR_CRU_ESCR2 0, 1, 2,
3, 4, 6
Shared See Section 18.18.1, “ESCR MSRs.”
3CDH 973 MSR_CRU_ESCR3 0, 1, 2,
3, 4, 6
Shared See Section 18.18.1, “ESCR MSRs.”
3E0H 992 MSR_CRU_ESCR4 0, 1, 2,
3, 4, 6
Shared See Section 18.18.1, “ESCR MSRs.”
3E1H 993 MSR_CRU_ESCR5 0, 1, 2,
3, 4, 6
Shared See Section 18.18.1, “ESCR MSRs.”
3FOH 1008 MSR_TC_PRECISE
_EVENT
0, 1, 2,
3, 4, 6
Shared See Section 18.18.1, “ESCR MSRs.”
3F1H 1009 MSR_PEBS_ENABLE 0, 1, 2,
3, 4, 6
Shared Precise Event-Based Sampling
(PEBS). (R/W)
Controls the enabling of precise
event sampling and replay tagging.
12:0 See Table A-14.
23:13 Reserved.
24 UOP Tag.
Enables replay tagging when set.
25 ENABLE_PEBS_MY_THR. (R/W)
Enables PEBS for the target logical
processor when set; disables PEBS
when clear (default).
See Section 18.19.3,
“IA32_PEBS_ENABLE MSR,” for an
explanation of the target logical
processor.
This bit is called ENABLE_PEBS in
IA-32 processors that do not
support Intel Hyper-Threading
Technology.
Table B-6. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)
Register
Address
Register Name
Fields and Flags
Model
Avail-
ability
Shared/
Unique
1
Bit Description
Hex Dec