Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 B-123
MODEL-SPECIFIC REGISTERS (MSRS)
When not implemented in the
processor, all reads and writes to
this MSR will cause a general-
protection exception.
480H 1152 IA32_VMX_BASIC 3, 4, 6 Unique Reporting Register of Basic VMX
Capabilities. (R/O). see Table B-2.
See Appendix G.1, “Basic VMX
Information”
481H 1153 IA32_VMX_PINBASED
_CTLS
3, 4, 6 Unique Capability Reporting Register of
Pin-based VM-execution
Controls. (R/O). see Table B-2.
See Appendix G.3, “VM-Execution
Controls”
482H 1154 IA32_VMX_
PROCBASED_CTLS
3, 4, 6 Unique Capability Reporting Register of
Primary Processor-based
VM-execution Controls. (R/O)
See Appendix G.3, “VM-Execution
Controls” and see Table B-2.
483H 1155 IA32_VMX_EXIT_CTLS 3, 4, 6 Unique Capability Reporting Register of
VM-exit Controls. (R/O)
See Appendix G.4, “VM-Exit
Controls” and see Table B-2.
484H 1156 IA32_VMX_ENTRY_
CTLS
3, 4, 6 Unique Capability Reporting Register of
VM-entry Controls. (R/O)
See Appendix G.5, “VM-Entry
Controls” and see Table B-2.
485H 1157 IA32_VMX_MISC 3, 4, 6 Unique Reporting Register of
Miscellaneous VMX Capabilities.
(R/O)
See Appendix G.6, “Miscellaneous
Data” and see Table B-2.
486H 1158 IA32_VMX_CR0_
FIXED0
3, 4, 6 Unique Capability Reporting Register of
CR0 Bits Fixed to 0. (R/O)
See Appendix G.7, “VMX-Fixed Bits
in CR0” and see Table B-2.
Table B-6. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)
Register
Address
Register Name
Fields and Flags
Model
Avail-
ability
Shared/
Unique
1
Bit Description
Hex Dec