Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

B-124 Vol. 3
MODEL-SPECIFIC REGISTERS (MSRS)
487H 1159 IA32_VMX_CR0_
FIXED1
3, 4, 6 Unique Capability Reporting Register of
CR0 Bits Fixed to 1. (R/O)
See Appendix G.7, “VMX-Fixed Bits
in CR0” and see Table B-2.
488H 1160 IA32_VMX_CR4_
FIXED0
3, 4, 6 Unique Capability Reporting Register of
CR4 Bits Fixed to 0. (R/O)
See Appendix G.8, “VMX-Fixed Bits
in CR4” and see Table B-2.
489H 1161 IA32_VMX_CR4_
FIXED1
3, 4, 6 Unique Capability Reporting Register of
CR4 Bits Fixed to 1. (R/O)
See Appendix G.8, “VMX-Fixed Bits
in CR4” and see Table B-2.
48AH 1162 IA32_VMX_VMCS_
ENUM
3, 4, 6 Unique Capability Reporting Register of
VMCS Field Enumeration. (R/O).
See Appendix G.9, “VMCS
Enumeration” and see Table B-2.
48BH 1163 IA32_VMX_
PROCBASED_CTLS2
3, 4, 6 Unique Capability Reporting Register of
Secondary Processor-based
VM-execution Controls. (R/O)
See Appendix G.3, “VM-Execution
Controls” and see Table B-2.
600H 1536 IA32_DS_AREA 0, 1, 2,
3, 4, 6
Unique DS Save Area. (R/W). see
Table B-2.
See Section 18.18.4, “Debug Store
(DS) Mechanism.”
680H 1664 MSR_LASTBRANCH
_0_FROM_LIP
3, 4, 6 Unique Last Branch Record 0. (R/W)
One of 16 pairs of last branch
record registers on the last branch
record stack (680H-68FH). This
part of the stack contains pointers
to the source instruction for one
of the last 16 branches,
exceptions, or interrupts taken by
the processor.
Table B-6. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)
Register
Address
Register Name
Fields and Flags
Model
Avail-
ability
Shared/
Unique
1
Bit Description
Hex Dec