Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

B-130 Vol. 3
MODEL-SPECIFIC REGISTERS (MSRS)
The MSRs listed in Table B-8 apply to Intel Xeon Processor 7100 series. These
processors can be detected by enumerating the deterministic cache parameter leaf of
CPUID instruction (with EAX = 4 as input) to detect the presence of the third level
cache, and with CPUID reporting family encoding 0FH, model encoding 6 (See CPUID
instruction for more details.). The performance monitoring MSRs listed in Table B-8
are shared between logical processors in the same core, but are replicated for each
core.
107CFH MSR_IFSB_SNPQ1 3, 4 Shared IFSB SNPQ Event Control
and Counter Register.
(R/W)
107D0H MSR_EFSB_DRDY0 3, 4 Shared EFSB DRDY Event Control
and Counter Register.
(R/W)
See Section 18.23,
“Performance Monitoring on
64-bit Intel Xeon Processor
MP with Up to 8-MByte L3
Cache” for details.
107D1H MSR_EFSB_DRDY1 3, 4 Shared EFSB DRDY Event Control
and Counter Register.
(R/W)
107D2H MSR_IFSB_CTL6 3, 4 Shared IFSB Latency Event Control
Register. (R/W)
See Section 18.23,
“Performance Monitoring on
64-bit Intel Xeon Processor
MP with Up to 8-MByte L3
Cache” for details.
107D3H MSR_IFSB_CNTR7 3, 4 Shared IFSB Latency Event
Counter Register. (R/W)
See Section 18.23,
“Performance Monitoring on
64-bit Intel Xeon Processor
MP with Up to 8-MByte L3
Cache.”
Table B-7. MSRs Unique to 64-bit Intel Xeon Processor MP with
Up to an 8 MB L3 Cache (Contd.)
Register Address
Register Name
Fields and Flags
Model
Avail-
ability
Shared/
Unique Bit Description