Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 18-75
DEBUGGING AND PERFORMANCE MONITORING
is generated when PEBS buffer is full. Software must reset the PEBS Index field
to the beginning of the PEBS buffer address to continue capturing PEBS records.
• PEBS Interrupt Threshold: This field specifies the threshold value to trigger a
performance interrupt and notify software that the PEBS buffer is nearly full. This
field is programmed with the linear address of the first byte of the PEBS record
within the PEBS buffer that represents the threshold record. After the processor
writes a PEBS record and updates PEBS Index, if the PEBS Index reaches the
threshold value of this field, the processor will generate a performance interrupt.
This is the same interrupt that is generated by a performance counter overflow,
as programmed in the Performance Monitoring Counters vector in the Local
Vector Table of the Local APIC. When a performance interrupt due to PEBS buffer
full is generated, the IA32_PERF_GLOBAL_STATUS.PEBS_Ovf bit will be set.
• PEBS CounterX Reset: This field allows software to set up PEBS counter
overflow condition to occur at a rate useful for profiling workload, thereby
generating multiple PEBS records to facilitate characterizing the profile the
execution of test code. After each PEBS record is written, the processor checks
each counter to see if it overflowed and was enabled for PEBS (the corresponding
bit in IA32_PEBS_ENABLED was set). If these conditions are met, then the reset
value for each overflowed counter is loaded from the DS Buffer Management
Area. For example, if counter IA32_PMC0 caused a PEBS record to be written,
then the value of “PEBS Counter 0 Reset” would be written to counter
IA32_PMC0. If a counter is not enabled for PEBS, its value will not be modified by
the PEBS assist.
Performance Counter Prioritization
Performance monitoring interrupts are triggered by a counter transitioning from
maximum count to zero (assuming IA32_PerfEvtSelX.INT is set). This same transi-
tion will cause PEBS hardware to arm, but not trigger. PEBS hardware triggers upon
detection of the first PEBS event after the PEBS hardware has been armed (a 0 to 1
transition of the counter). At this point, a PEBS assist will be undertaken by the
processor.
Performance counters (fixed and general-purpose) are prioritized in index order. That
is, counter IA32_PMC0 takes precedence over all other counters. Counter
IA32_PMC1 takes precedence over counters IA32_PMC2 and IA32_PMC3, and so on.
This means that if simultaneous overflows or PEBS assists occur, the appropriate
action will be taken for the highest priority performance counter. For example, if
IA32_PMC1 cause an overflow interrupt and IA32_PMC2 causes an PEBS assist
simultaneously, then the overflow interrupt will be serviced first.
The PEBS threshold interrupt is triggered by the PEBS assist, and is by definition
prioritized lower than the PEBS assist. Hardware will not generate separate interrupts
for each counter that simultaneously overflows. General-purpose performance
counters are prioritized over fixed counters.
If a counter is programmed with a precise (PEBS-enabled) event and programmed to
generate a counter overflow interrupt, the PEBS assist is serviced before the counter
overflow interrupt is serviced. If in addition the PEBS interrupt threshold is met, the