Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 B-153
MODEL-SPECIFIC REGISTERS (MSRS)
1DDH 477 MSR_LER_TO_LIP Last Exception Record To Linear IP. (R)
This area contains a pointer to the target of the
last branch instruction that the processor
executed prior to the last exception that was
generated or the last interrupt that was handled.
See Section 18.9, “Last Branch, Interrupt, and
Exception Recording (Pentium M Processors)” and
Section 18.10.2, “Last Branch and Last Exception
MSRs.”
1DEH 478 MSR_LER_FROM_LIP Last Exception Record From Linear IP. (R)
Contains a pointer to the last branch instruction
that the processor executed prior to the last
exception that was generated or the last interrupt
that was handled.
See Section 18.9, “Last Branch, Interrupt, and
Exception Recording (Pentium M Processors)” and
Section 18.10.2, “Last Branch and Last Exception
MSRs.”
2FFH 767 IA32_MTRR_DEF_
TYPE
Default Memory Types. (R/W)
Sets the memory type for the regions of physical
memory that are not mapped by the MTRRs.
See Section 10.11.2.1, “IA32_MTRR_DEF_TYPE
MSR.”
400H 1024 IA32_MC0_CTL See Section 14.3.2.1, “IA32_MCi_CTL MSRs.”
401H 1025 IA32_MC0_STATUS See Section 14.3.2.2, “IA32_MCi_STATUS MSRS.”
402H 1026 IA32_MC0_ADDR See Section 14.3.2.3., “IA32_MCi_ADDR MSRs”.
The IA32_MC0_ADDR register is either not
implemented or contains no address if the ADDRV
flag in the IA32_MC0_STATUS register is clear.
When not implemented in the processor, all reads
and writes to this MSR will cause a general-
protection exception.
404H 1028 IA32_MC1_CTL See Section 14.3.2.1, “IA32_MCi_CTL MSRs.”
405H 1029 IA32_MC1_STATUS See Section 14.3.2.2, “IA32_MCi_STATUS MSRS.”
Table B-10. MSRs in Pentium M Processors (Contd.)
Register
Address
Register Name Bit Description
Hex Dec