Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 B-159
MODEL-SPECIFIC REGISTERS (MSRS)
8BH 139 BIOS_SIGN/BBL_CR_D3[6
3:0]
BIOS Update Signature Register or Chunk 3 data
register D[63:0].
Used to write to and read from the L2 depending
on the usage model
C1H 193 PerfCtr0 (PERFCTR0)
C2H 194 PerfCtr1 (PERFCTR1)
FEH 254 MTRRcap
116 278 BBL_CR_ADDR [63:0]
BBL_CR_ADDR [63:32]
BBL_CR_ADDR [31:3]
BBL_CR_ADDR [2:0]
Address register: used to send specified address
(A31-A3) to L2 during cache initialization accesses.
Reserved,
Address bits [35:3]
Reserved Set to 0.
118 280 BBL_CR_DECC[63:0] Data ECC register D[7:0]: used to write ECC and
read ECC to/from L2
119 281 BBL_CR_CTL
BL_CR_CTL[63:22]
BBL_CR_CTL[21]
Control register: used to program L2 commands to
be issued via cache configuration accesses
mechanism. Also receives L2 lookup response
Reserved
Processor number
2
Disable = 1
Enable = 0
Reserved
BBL_CR_CTL[20:19]
BBL_CR_CTL[18]
BBL_CR_CTL[17]
BBL_CR_CTL[16]
BBL_CR_CTL[15:14]
BBL_CR_CTL[13:12]
BBL_CR_CTL[11:10]
BBL_CR_CTL[9:8]
BBL_CR_CTL[7]
BBL_CR_CTL[6:5]
User supplied ECC
Reserved
L2 Hit
Reserved
State from L2
Modified - 11,Exclusive - 10, Shared - 01, Invalid -
00
Way from L2
Way 0 - 00, Way 1 - 01, Way 2 - 10, Way 3 - 11
Way to L2
Reserved
State to L2
Table B-11. MSRs in the P6 Family Processors (Contd.)
Register
Address
Register Name Bit Description
Hex Dec