Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 E-3
INTERPRETING MACHINE-CHECK ERROR CODES
Model specific
errors
27-25 Bus queue error type 000 for BQ_ERR_HARD_TYPE error
001 for BQ_ERR_DOUBLE_TYPE error
010 for BQ_ERR_AERR2_TYPE error
100 for BQ_ERR_SINGLE_TYPE error
101 for BQ_ERR_AERR1_TYPE error
Model specific
errors
28 FRC error 1 if FRC error active
29 BERR 1 if BERR is driven
30 Internal BINIT 1 if BINIT driven for this processor
31 Reserved Reserved
Other
information
32-34 Reserved Reserved
35 External BINIT 1 if BINIT is received from external bus.
36 Response parity error This bit is asserted in IA32_MCi_STATUS if this
component has received a parity error on the
RS[2:0]# pins for a response transaction. The
RS signals are checked by the RSP# external
pin.
37 Bus BINIT This bit is asserted in IA32_MCi_STATUS if this
component has received a hard error response
on a split transaction one access that has
needed to be split across the 64-bit external
bus interface into two accesses).
38 Timeout BINIT This bit is asserted in IA32_MCi_STATUS if this
component has experienced a ROB time-out,
which indicates that no micro-instruction has
been retired for a predetermined period of
time.
A ROB time-out occurs when the 15-bit ROB
time-out counter carries a 1 out of its high
order bit. The timer is cleared when a micro-
instruction retires, an exception is detected by
the core processor, RESET is asserted, or when
a ROB BINIT occurs.
Table E-2. Incremental Decoding Information: Processor Family 06H
Machine Error Codes For Machine Check (Contd.)
Type Bit No. Bit Function Bit Description