Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

E-4 Vol. 3
INTERPRETING MACHINE-CHECK ERROR CODES
The ROB time-out counter is prescaled by the
8-bit PIC timer which is a divide by 128 of the
bus clock the bus clock is 1:2, 1:3, 1:4 of the
core clock). When a carry out of the 8-bit PIC
timer occurs, the ROB counter counts up by
one. While this bit is asserted, it cannot be
overwritten by another error.
39-41 Reserved Reserved
42 Hard error This bit is asserted in IA32_MCi_STATUS if this
component has initiated a bus transactions
which has received a hard error response. While
this bit is asserted, it cannot be overwritten.
43 IERR This bit is asserted in IA32_MCi_STATUS if this
component has experienced a failure that
causes the IERR pin to be asserted. While this
bit is asserted, it cannot be overwritten.
44 AERR This bit is asserted in IA32_MCi_STATUS if this
component has initiated 2 failing bus
transactions which have failed due to Address
Parity Errors AERR asserted). While this bit is
asserted, it cannot be overwritten.
45 UECC The Uncorrectable ECC error bit is asserted in
IA32_MCi_STATUS for uncorrected ECC errors.
While this bit is asserted, the ECC syndrome
field will not be overwritten.
46 CECC The correctable ECC error bit is asserted in
IA32_MCi_STATUS for corrected ECC errors.
47-54 ECC syndrome The ECC syndrome field in IA32_MCi_STATUS
contains the 8-bit ECC syndrome only if the
error was a correctable/uncorrectable ECC error
and there wasn't a previous valid ECC error
syndrome logged in IA32_MCi_STATUS.
A previous valid ECC error in IA32_MCi_STATUS
is indicated by IA32_MCi_STATUS.bit45
uncorrectable error occurred) being asserted.
After processing an ECC error, machine-check
handling software should clear
IA32_MCi_STATUS.bit45 so that future ECC
error syndromes can be logged.
Table E-2. Incremental Decoding Information: Processor Family 06H
Machine Error Codes For Machine Check (Contd.)
Type Bit No. Bit Function Bit Description