Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 E-7
INTERPRETING MACHINE-CHECK ERROR CODES
Model specific
errors
27-25 Bus queue error type 000 for BQ_ERR_HARD_TYPE error
001 for BQ_ERR_DOUBLE_TYPE error
010 for BQ_ERR_AERR2_TYPE error
100 for BQ_ERR_SINGLE_TYPE error
101 for BQ_ERR_AERR1_TYPE error
Model specific
errors
28 MCE Driven 1 if MCE is driven
29 MCE Observed 1 if MCE is observed
30 Internal BINIT 1 if BINIT driven for this processor
31 BINIT Observed 1 if BINIT is observed for this processor
Other
information
32-33 Reserved Reserved
34 PIC and FSB data
parity
Data Parity detected on either PIC or FSB
access
35 Reserved Reserved
36 Response parity error This bit is asserted in IA32_MCi_STATUS if this
component has received a parity error on the
RS[2:0]# pins for a response transaction. The
RS signals are checked by the RSP# external
pin.
37 FSB address parity Address parity error detected:
1 = Address parity error detected
0 = No address parity error
38 Timeout BINIT This bit is asserted in IA32_MCi_STATUS if this
component has experienced a ROB time-out,
which indicates that no micro-instruction has
been retired for a predetermined period of
time.
A ROB time-out occurs when the 15-bit ROB
time-out counter carries a 1 out of its high
order bit. The timer is cleared when a micro-
instruction retires, an exception is detected by
the core processor, RESET is asserted, or when
a ROB BINIT occurs.
Table E-4. Incremental Bus Error Codes of Machine Check for Processors Based on
Intel Core Microarchitecture
Type Bit No. Bit Function Bit Description