Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 18-79
DEBUGGING AND PERFORMANCE MONITORING
The layout of MSR_OFFCORE_RSP_0 is shown in Figure 18-28. Bits 7:0 specifies the
request type of a transaction request to the uncore. Bits 15:8 specifies the response
of the uncore subsystem.
Table 18-23. Off-Core Response Event Encoding
Event code in
IA32_PERFEVTSELx
Mask Value in
IA32_PERFEVTSELx Required Off-core Response MSR
0xB7 0x01 MSR_OFFCORE_RSP_0 (address 0x1A6)
Figure 18-28. Layout of MSR_OFFCORE_RSP_0 MSR to Configure Off-core Response
Events
Table 18-24. MSR_OFFCORE_RSP_Z Bit Field Definition
Bit Name Offset Description
DMND_DATA_RD 0 (R/W). Counts the number of demand and DCU prefetch data reads
of full and partial cachelines as well as demand data page table
entry cacheline reads. Does not count L2 data read prefetches or
instruction fetches.
RESPONSE TYPE — NON_DRAM (R/W)
RESPONSE TYPE — LOCAL_DRAM (R/W)
RESPONSE TYPE — REMOTE_DRAM (R/W)
RESPONSE TYPE — REMOTE_CACHE_FWD (R/W)
87 0
RESPONSE TYPE — RESERVED
11 312 1
Reserved
63
2
495610131415
RESPONSE TYPE — OTHER_CORE_HITM (R/W)
RESPONSE TYPE — OTHER_CORE_HIT_SNP (R/W)
RESPONSE TYPE — UNCORE_HIT (R/W)
REQUEST TYPE — OTHER (R/W)
REQUEST TYPE — PF_IFETCH (R/W)
REQUEST TYPE — PF_RFO (R/W)
REQUEST TYPE — PF_DATA_RD (R/W)
REQUEST TYPE — WB (R/W)
REQUEST TYPE — DMND_IFETCH (R/W)
REQUEST TYPE — DMND_RFO (R/W)
REQUEST TYPE — DMND_DATA_RD (R/W)
RESET Value — 0x00000000_00000000